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Design Verification Engineer (FUSA)

Design Verification Engineer (FUSA)

Location:

Hyderabad

Roles and Responsibilities:

  • Experience in FuSa Verification
  • Experience in Verilog and System Verilog languages
  • ISO 26262, Functional Safety,
  • Experience in UVM
  • Exposure to ISO 26262, fault injection, or diagnostic coverage analysis is desirable for FuSa track

Requirements:

Skills Required:

Verilog and System Verilog languages

Employement Type:

Full Time

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